1. Field of the Invention
The present invention relates to interface circuits, and more particularly to translating interface circuits and receivers, and even more particularly to high speed interface receivers with low voltage differential input signals (LVDS) and complementary, low skew CMOS differential output signals.
2. Background Information
Low voltage differential signals are common for high speed signal transmission. Saturation effects are avoided and power is limited thereby encouraging the use of LVDS, and, since low voltage signals are prone to noise, differential signals, where the noise is common to both signals, generally will overcome this problem.
However, since common mode signals will occur, LVDS circuits are designed to accept differential signals that ride on a common mode level that, in the best case will range from the low power, or ground, rail to the Vcc power rail.
Designs for such translators strive for low power dissipation, increased speed, reduced edge delays, reduced jitter, reduced skew, and for efficient in the use of die area. Often the output of the receiver requires a TTL or CMOS logic level, so such designs also strive for high to low rail to rail outputs.
U.S. Pat. Nos. 6,275,073 B1, 6,252,432 B1 and 6,236,269 B1 set out a high speed differential input circuits that operates over a wide input common mode range but each provides only a single ended output. In these patents the differential input signals are each input to the gates of both an NMOS and a PMOS transistor so that NMOS will handle common mode voltages up to within about 200 millivolts of the high power rail and the PMOS down to within about 200 millivolts of the ground.
Notice that in the above prior art patents, the circuitry shown is not symmetrical. That is the differential inputs signal paths to the outputs is not the same for the two inputs. This lack of symmetry adds to the skew and jitter of these circuits.
There is a need to provide in many applications both a signal and its complement. The prior art circuits require a series inverter delay to complement the signal. In such cases the complement signal is offset from the output signal by the gate delay on each signal edge. The complement will have an inherent skew and non-symmetry due to the need for a series inverter.
There is a need for a differential low voltage receiver with a wide common mode range that provides complementary outputs with improved skew and jitter performance.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.
In view of the foregoing background discussion, the present invention provides a high speed, low power, differential receiver that provides complementary TTL and CMOS compatible differential outputs, and that demonstrates lower skew and jitter, and that accepts rail to rail common mode inputs while providing rail to rail complementary outputs.
Use of precise symmetry, duplicated circuitry and therefore loads along each of the differential input signal paths and full differential circuitry throughout the invention provides for the objective operational improvements of the present invention. Inspection of a preferred embodiment in FIG. 3 clearly shows this symmetry.